1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a non-volatile semiconductor memory device including memory cells each having a duplicate gate structure in which a floating gate and a control gate are stacked, such as an EPROM, an EEPROM or a flash memory, and to a method of producing the same.
2. Description of the Prior Art
FIGS. 1A through 1D schematically illustrating steps of producing a memory cell in a flash memory according to prior art.
At the first step (see FIG. 1A), an oxide film as an insulation film 2 for device isolation is deposited about 400 nm to 800 nm thick on a semiconductor substrate (e.g., a p-type silicon substrate) 1 by, for example, thermal oxidation, and an oxide film 3 to be a first gate insulation film is further deposited about 10 nm thick by thermal oxidation. Then, a polysilicon film 4 to be a floating gate is formed approximately 130 nm thick on the entire surface of the resultant structure, and phosphorus (P) or the like as an impurity is doped into the polysilicon film 4. Then, an oxide film 5 to be a second gate insulation film is deposited about 20 nm thick by thermal oxidation after which a polysilicon film 6 to be a control gate is formed approximately 150 nm thick on the entire surface of the resultant structure, and phosphorus (P) or the like as an impurity is doped into the polysilicon film 6.
At the next step (see FIG. 1B), resist patterning (coating a resist on) of the control gate is carried out by using photolithography, and the polysilicon film 6, the oxide film 5, the polysilicon film 4 and the oxide film 3 are etched with the resist used as a mask. Then, the resist is removed. This completes a lamination structure in which the first gate insulation film 3G, floating gate 4G, the second gate insulation film 5G and the control gate 6G are stacked in order on the semiconductor substrate 1 as illustrated.
At the subsequent step (see FIG. 1C), to make a source region of a high withstand voltage, as an impurity, phosphorus (P) or the like whose conductivity type is opposite to that of the semiconductor substrate 1 is lightly doped using photolithography, thereby forming an n-type diffusion layer 7, and as another impurity, arsenic (As) or the like whose conductivity type is opposite to that of the semiconductor substrate 1 is heavily doped by photolithography, thereby forming an n-type diffusion layer (source region) 8S and an n-type diffusion layer (drain region) 8D. Next, an oxide film as an insulation film is grown about 200 nm thick on the entire surface of the resultant structure by chemical vapor deposition (CVD), then anisotropic dry etching is performed to form a side-wall insulation film 9 on the side walls of the lamination structure (3G, 4G, 5G and 6G).
At the final step (see FIG. 1D), after an interlayer insulation film LS is formed by CVD, contact holes which respectively reach the source region 8S, the drain region 8D and the control gate 6G are formed, and electrode wires WS, WD and WG are so formed as to fill the individual contact holes. This completes the memory cell structure.
The write operation (programming) and erasing operation of a non-volatile semiconductor memory device which has memory cells that are fabricated in the above-described manner are implemented as follows. In the write mode, a voltage is applied between the control gate and the drain region in such a way as to generate a positive electric field therebetween. This causes hot electrons to be generated from the drain region. The electrons are injected into the floating gate to write information. In the erasure mode, a voltage is applied between the control gate and the source region in such a way as to generate a negative electric field therebetween, and electrons are drained into the source region from the floating gate through the oxide film (first gate insulation film) by the F-N (Fowler-Nordheim) tunnel current, thereby erasing information.
Since the write operation and erasing operation of a non-volatile semiconductor memory device are executed respectively by injection of electrons into the floating gate and draining of electrons from the floating gate, as mentioned above, their operation characteristics are influenced by the voltage that is applied to the floating gate. The floating gate voltage that affects the operation characteristics will now be described with reference to FIG. 2 which shows the conceptual structure of a memory cell having a duplicate gate structure.
As shown in FIG. 2, assuming that the capacitance between the floating gate and the substrate is C1; the capacitance between the floating gate and the control gate is C2; the capacitance between the floating gate and the drain region is C3; the capacitance between the floating gate and the source region is C4; the drain voltage is V.sub.D ; the source voltage is V.sub.S ; the control gate voltage is V.sub.CG ; the floating gate voltage is V.sub.FG ; the area of the overlapping portion of the floating gate over the source region is S; an electric field which is applied to the oxide film (first gate insulation film) between the floating gate and the source region in the erasure mode is E.sub.OX ; and the F-N tunnel current which flows into the source region from the floating gate in the erasure mode is I.sub.FN, the floating gate voltage in the write mode and the floating gate voltage and the F-N tunnel current I.sub.FN in the erasure mode are respectively expressed by following equations (1), (2) and (3). EQU V.sub.FG(W) ={C2/(C1+C2+C3+C4)}V.sub.CG +{C3/(C1+C2+C3+C4)}V.sub.D (1) EQU V.sub.FG(E) ={C2/(C1+C2+C3+C4)}V.sub.CG +{C4/(C1+C2+C3+C4)}V.sub.S (2) EQU I.sub.FN =A.sub.FN SE.sub.OX.sup.2 exp(B.sub.FN /E.sub.OX) (3)
where A.sub.FN and B.sub.FN are constants.
Assuming that the control gate voltage V.sub.CG and the drain voltage V.sub.D are constant, the equation (1) shows that the floating gate voltage V.sub.FG(W) in the write mode becomes higher as the capacitances C2 and C3 get larger. The higher this floating gate voltage V.sub.FG(W) gets, the greater the amount of electrons to be injected into the floating gate becomes, so that the write time can be shortened. It is therefore preferable that the floating gate voltage V.sub.FG(W) is high. This requires that the capacitances C2 and C3 should be made large.
Likewise, assuming that the control gate voltage V.sub.CG and the source voltage V.sub.S are constant, it is apparent from the equation (2) that the floating gate voltage V.sub.FG(E) in the erasure mode becomes higher as the capacitance C2 gets greater. The higher this floating gate voltage V.sub.FG(E) gets, the greater the amount of electrons to be drained from the floating gate becomes, allowing the erasure time to be shortened. It is therefore preferable that the floating gate voltage V.sub.FG(E) is high. This requires that the capacitance C2 should be made large.
Also, assuming that the electric field E.sub.OX to be applied to the first gate insulation film is constant, it is apparent from the equation (3) that the larger the area S of the overlapping portion of the floating gate over the source region gets, the greater the F-N tunnel current I.sub.FN becomes, thereby permitting the erasure time to be shortened. It is thus preferable that the overlapping area S is large.
It should be understood from FIG. 2 that the capacitance C2 is proportional to the size of the opposing area of the floating gate to the control gate and is inversely proportional to the thickness of the second gate insulation film. The capacitance C3 is proportional to the area of the floating gate that overlaps the drain region and is inversely proportional to the thickness of the first gate insulation film. The F-N tunnel current I.sub.FN is proportional to the area (S) of the floating gate that overlaps the source region.
To increase the capacitances C2 and C3 and the F-N tunnel current I.sub.FN, therefore, it is necessary to make the individual gate insulation films thinner or to increase the area of the floating gate overlapping the drain/source region or the opposing area of the floating gate with respect to the control gate. In this case, since there is a limit to making the individual gate insulation films thinner from the viewpoint of securing the insulation property, an approach to increase the area of the floating gate that overlaps the drain/source region is rather effective.
According to the above prior art (see FIGS. 1A to 1D), since the side-wall insulation film 9 is formed on the side walls of the floating gate 4G, the area of the floating gate 4G that overlaps the source region 8S and the drain region 8D, which are formed on the semiconductor substrate 1 so as to be self-aligned with the floating gate 4G, is not large enough. That is, the size of the capacitance C3 and the area S of the overlapping portion of the floating gate over the source region are not sufficiently large, but are rather small.
When the capacitances C2 and C3 are small, it is apparent from the equation (1) that the floating gate voltage V.sub.FG(W) in the write mode decreases relatively with respect to the same voltages V.sub.CG and V.sub.D. As a result, the efficiency of electron injection into the floating gate (i.e., the writing efficiency) decreases, undesirably making the write time longer.
When the capacitance C2 is small and the area (S) of the overlapping portion of the floating gate over the source region is not large enough, it is apparent from the equations (2) and (3) that the floating gate voltage V.sub.FG(E) in the erasure mode is lowered relatively with respect to the same voltages V.sub.CG and V.sub.S. So does the F-N tunnel current I.sub.FN. Consequently, the efficiency of draining electrons from the floating gate into the source region by the F-N tunnel current I.sub.FN (i.e., the erasing efficiency) gets lower, undesirably making the erasure time longer.
Also, according to the above prior art, increasing the capacitance C2 between the floating gate and the control gate requires that the opposing areas of both gates should be made larger. This results in an increase in the area of each memory cell and eventually leads to a reduction in the integration scale. Thus, some improvement should be made on that approach.
Further, because the capacitances C2 and C3 and the area (S) of the floating gate that overlaps the source region are insufficient, increasing the floating gate voltages V.sub.FG(W) and V.sub.FG(E) to improve the write efficiency and erasure efficiency requires that the individual voltages V.sub.CG, V.sub.D and V.sub.S to be applied to each memory cell should be increased. This undesirably results in an increase in the power consumption of a non-volatile semiconductor memory device.